Field of the Invention
The invention relates to an integrated memory with redundancy. The invention also relates to a method for repairing an integrated memory.
It is generally known to replace defective memory cells of a memory with redundant memory cells and to repair the memory in this way. In this case, the redundant memory cells are arranged either along redundant word lines or redundant bit lines. Wada (U.S. Pat. No. 5,568,432) describes, by way of example, an integrated memory having a redundant bit line that is provided for replacing one of the normal bit lines along which the normal memory cells are arranged. The normal bit line is assigned to a sense amplifier which, when the memory cells are read, amplifies the information stored in said memory cells and supplies it to a point outside the memory. In a redundancy situation, that is to say after implementation of the replacement of the normal bit line by the redundant bit line, a redundancy shift circuit ensures that the redundant bit line, instead of the normal bit line, is connected to the sense amplifier thereof.
Wada (U.S. Pat. No. 5,568,432) additionally describes another redundancy concept in which the redundant bit line is already assigned a redundant sense amplifier that is present in addition to the normal sense amplifiers of the normal bit lines. In the redundancy situation, the redundant bit line with its redundant sense amplifier replaces the defective normal bit line and its normal sense amplifier.
It is accordingly an object of the invention to provide an integrated memory with redundancy and method for repairing an integrated memory that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has bit lines that are connected to sense amplifiers, in which memory defects are repaired in a different way. With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated memory. The integrated memory includes normal memory cells. A normal bit line connects to the normal memory cells for transferring data between the normal memory cells. A normal sense amplifier is included for amplifying data read from the normal memory cells. A line connects the normal sense amplifier to the normal bit line. A data line connects to the normal sense amplifier. The integrated memory includes a redundant sense amplifier for replacing the normal sense amplifier in a redundancy situation. The redundant sense amplifier connects to the line and to the data line and amplifies data read from the normal memory cells in the redundancy situation.
With the objects of the invention in view, there is also provided a method for repairing an integrated memory. The method includes testing the normal sense amplifier and the normal bit line. If the normal sense amplifier is defective, the next step is replacing the normal sense amplifier with the redundant sense amplifier. If at least one of the normal bit line and at least one of the normal memory cells is defective, the next step is replacing the bit line with the redundant bit line. The next step is writing to and reading from the normal memory cells via the normal sense amplifier to test the normal memory cells of the normal bit line. If the normal memory cells are defective, the next step is replacing the normal bit line with the redundant bit line. The next step is writing to and reading from the redundant memory cells via the normal sense amplifier to test the redundant memory cells of the redundant bit line. If the redundant memory cells are defective, the next step is reversing the replacement of the normal bit line with the redundant bit line and replacing the normal sense amplifier with the redundant sense amplifier.
With the objects of the invention in view, there is also provided a method for repairing an integrated memory. The first step is testing the normal sense amplifier and the normal bit line with the normal memory cells connected thereto. If the normal sense amplifier is defective, the next step is replacing the normal sense amplifier with the redundant sense amplifier. If at least one of the normal bit line and at least one of the normal memory cells is defective, the next step is replacing the bit line with the redundant bit line. The next step is writing to and reading from the normal memory cells via the normal sense amplifier to test the normal memory cells of the normal bit line. If the normal memory cells are defective, the next step is replacing the normal sense amplifier with the redundant sense amplifier. The next step is writing to and reading from the normal memory cells via the redundant sense amplifier to test the normal memory cells of the normal bit line. If the normal memory cells remain defective, the next step is reversing the replacement of the normal sense amplifier with the redundant sense amplifier by replacing the normal bit line with the redundant bit line.
The integrated memory according to the invention has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and to a data line. The normal sense amplifier serves for amplifying data read from the normal memory cells. Furthermore, the integrated memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected to the line and to the data line. In the redundancy situation, the redundant sense amplifier serves for amplifying the data read from the normal memory cells.
The invention is based on the following insights. The defects that are detected during read-out via a normal bit line are for the most part attributable to defects of the bit line itself or of the normal memory cells connected to it. Nevertheless, the situation also can occur when the normal sense amplifier connected to the bit line is defective but the bit line with the memory cells connected thereto is intact. In such a situation, replacing the intact bit line with a redundant bit line would not contribute to successful repair of the memory. On the other hand, if both the defective sense amplifier and the bit line connected to it were replaced by redundant elements, even though only the normal sense amplifier is defective, a disproportionately high outlay would result compared with the solution proposed here. The invention replaces a defective normal sense amplifier with a redundant sense amplifier. The normal bit line connected to the defective sense amplifier need not be replaced by a redundant bit line at the same time. If only the normal sense amplifier is defective, but not the normal bit line, the normal bit line still can be accessed via the redundant sense amplifier in the redundancy situation.
According to a development of the invention, the integrated memory has a redundant bit line. The redundant bit line is provided for replacing the normal bit line and is likewise connected to the line. In the event of the normal bit line being replaced by the redundant bit line, data from or to redundant memory cells connected to the redundant bit line is transferred either via the normal or the redundant sense amplifier. This depends on whether the normal sense amplifier has also been replaced by the redundant sense amplifier.
This has the advantage that, independently of one another, it is possible to repair both a defect of the normal sense amplifier by using the redundant sense amplifier and a defect of the normal bit line by using the redundant bit line. This ensures a high degree of flexibility. Moreover, the existing redundant resources (redundant sense amplifier and redundant bit line) can be used the most effectively.
In addition or as an alternative to the embodiments just mentioned, the integrated memory, according to a development, has a further redundant bit line. The further redundant bit line is provided for replacing the normal bit line and is connected to the data line via a further redundant sense amplifier. In this case, the redundant sense amplifier can repair a defect of the normal sense amplifier and replacing the normal bit line and its normal sense amplifier can repair a defect of the normal bit line by the redundant further bit line and the further redundant sense amplifier.
According to a development, the integrated memory has two programmable connection elements. A first programmable connects the line to the normal sense amplifier. A second programmable connection element connects to the redundant sense amplifier. The connection elements are electrically conductive or electrically nonconductive depending on their programming state.
In addition or as an alternative to these connection elements, the integrated memory, according to a development, has two programmable connection elements. The normal sense amplifier connects via the first programmable connection element to the data line. The redundant sense amplifier connects via the second programmable connection element to the data line. These connection elements are likewise electrically conductive or electrically nonconductive depending on their programming state. By corresponding programming, the connection elements enable the normal or redundant sense amplifiers to be electrically decoupled from the line or from the data line depending on whether or not the redundancy situation is present. As a result, malfunctions are avoided and the capacitive loading for the respectively activated sense amplifier is minimized.
Reversibly-programmable programmable connection elements are particularly advantageous because their programming can be reversed again or cancelled. In the context of the repair method, reversibly-programmable programmable conection elements enable a trial replacement either of the normal sense amplifier or of the normal bit line. And, this repair can be reversed in the case where a defect is still ascertained even afterward. The defect that has now been localized can thereupon be repaired using the respective other type of redundancy which has not hitherto been employed.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory with redundancy, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.